This guide covers: the five custom IC implementation types and how to choose between them (POINT 01), six business reasons companies invest in custom silicon (POINT 02), NRE costs by process node and volume requirements (POINT 03), the 12-step ASIC development flow (POINT 04), the fabless/foundry/IDM industry model (POINT 05), design houses and IP vendor ecosystem (POINT 06), EDA tooling (POINT 07), the procurement team's role in an ASIC programme (POINT 08), and four risk categories with mitigation strategies (POINT 09).
Custom IC development spans a wide range of implementation approaches — from the maximum performance and cost optimisation of full-custom ASICs to the rapid time-to-hardware of FPGAs. Selecting the right approach requires matching the design's volume, performance requirements, schedule constraints, and NRE budget to the trade-offs each type offers.
FULL CUSTOM
Full-Custom ASIC
Designed at the transistor level — every transistor manually sized, placed, and routed for absolute optimisation of performance, power, and silicon area. Maximum design effort and NRE. Appropriate only for the highest-performance, highest-volume chips where the performance delta justifies the investment.
Used in: mobile SoCs (Apple A-series), CPUs, GPU compute units, high-speed SerDes, memory cells.
STANDARD CELL
Standard Cell ASIC
Designed using the foundry-provided standard cell library (pre-characterised logic gates, flip-flops, memory compilers). Automated place-and-route handles physical implementation. Substantially lower design effort than full-custom while achieving within 20–40% of its performance. The dominant ASIC approach for the majority of custom IC programmes.
Best balance of performance, NRE cost, and development time for most ASIC programmes.
STRUCTURED ASIC
Structured ASIC
Uses a pre-configured base array — only the metal interconnect layers are customised per design. Requires far fewer custom mask layers than standard cell (2–4 metal layers vs. 30+ full layers). Substantially lower NRE than standard cell ASIC. Performance between FPGA and standard cell. Best for medium-volume designs where full standard cell NRE is difficult to justify.
Suited to: 50K–500K unit/year volume range where FPGA unit cost is too high but full ASIC NRE is too large.
FPGA
Field-Programmable Gate Array
Reprogrammable after manufacture — logic functionality is defined by the configuration loaded into the device. No custom masks required. Development time from RTL to working hardware can be weeks. Higher per-unit cost than ASIC at volume. Used for: product development (FPGA prototyping before ASIC tapeout), low-to-medium volume products, applications requiring in-field firmware updates.
FPGA unit cost typically 5–20× higher than equivalent ASIC at volume — the break-even volume determines the migration decision.
MPSoC
Multi-Processor SoC / SoC FPGA
Integrates multiple processor cores (ARM Cortex-A, RISC-V), programmable logic (FPGA fabric), memory controllers, and peripherals in a single die. Xilinx Zynq (now AMD) and Intel/Altera SoC FPGA are the standard representatives. Combines processor software flexibility with programmable hardware acceleration — enabling system designs that would otherwise require multiple separate chips.
Used in: industrial control, radar/SDR, medical imaging, automotive ADAS, high-performance embedded computing.
Decision framework — FPGA vs ASIC: The primary quantitative question is the volume break-even point: at what annual production volume does the ASIC NRE investment recover in unit cost savings versus continuing with FPGA? Calculate: (ASIC NRE cost) ÷ (FPGA unit cost − ASIC unit cost) = break-even volume. At volumes above break-even, ASIC has lower total cost of ownership. Below break-even, FPGA or structured ASIC is preferable unless performance requirements mandate ASIC regardless of cost. Most standard cell ASIC programmes require annual volumes of 100,000 units or more to justify NRE recovery at accessible process nodes.
REASON 1
Performance beyond standard components
When no standard IC can deliver the required combination of processing speed, power consumption, and silicon area, custom ASIC is the only option. This is the reason Apple designs its own A-series and M-series SoCs — the performance-per-watt advantage over any available standard component is decisive for the product experience.
REASON 2
Integration of multiple functions into one chip
Combining functions that currently require five separate ICs into one custom ASIC reduces PCB area, eliminates inter-chip routing, reduces power consumption, and simplifies the BOM. Integration-driven ASIC programmes often have straightforward ROI calculations based on BOM cost reduction and PCB area savings alone.
REASON 3
Competitive differentiation
A competitor who uses only standard components can be replicated by any competitor who uses the same components. A product built around a proprietary ASIC has a hardware differentiation that cannot be replicated by purchasing the same parts from the same distributors. Apple, Qualcomm, Google (Tensor), and Amazon (Trainium) have all built significant competitive advantages through proprietary silicon.
REASON 4
Total BOM cost reduction at scale
At sufficient volume, a custom ASIC that replaces multiple standard components can achieve lower total BOM cost than the standard component approach. The custom chip's silicon cost is lower than the sum of the standard components it replaces, and the simplified PCB design reduces manufacturing cost further. This calculation requires honest volume projections and NRE amortisation over realistic product lifetimes.
REASON 5
Intellectual property protection
Internalising key algorithmic or signal processing functions in a custom ASIC — rather than implementing them in software on a standard MCU — makes reverse engineering substantially harder. The algorithm is embedded in the silicon structure of a custom die that is extremely difficult and expensive to analyse. For products where the core IP is the algorithm (encryption, imaging, sensing), ASIC implementation provides hardware-level IP protection that software implementation cannot.
REASON 6
Long-term supply independence
Standard component EOL is a chronic supply chain risk for products with long service lives. A custom ASIC designed for a specific product is immune to third-party EOL decisions — supply continuity is entirely within the control of the product company through its foundry relationship. For products with 15–20 year service life requirements (industrial, medical, infrastructure), this supply independence has significant financial and contractual value.
NRE (Non-Recurring Engineering) is the one-time investment required to develop and tapeout a custom ASIC. It primarily represents the cost of the mask set (the photomasks used to fabricate the wafers), EDA tool licensing, IP purchases, and design engineering labour. NRE does not recur after the initial tapeout — unless a design re-spin (respin) is required to correct a silicon bug.
| Process Node | Approx. NRE Range (mask set + tooling) | Min volume to recover NRE | Typical applications |
|---|
| 180nm / 130nm | $200K–$1M USD | ~50K–200K units/year | Power management ICs, simple mixed-signal, low-speed digital control |
| 65nm / 55nm | $500K–$3M USD | ~100K–500K units/year | Low-power IoT SoCs, industrial control, sensor interface |
| 40nm / 28nm | $2M–$10M USD | ~500K–2M units/year | Complex digital SoCs, networking, storage controllers, mid-range wireless |
| 16nm / 12nm | $10M–$40M USD | ~2M–10M units/year | High-performance compute, 5G modem, AI inference accelerators |
| 7nm | $50M–$200M USD | ~10M+ units/year | Mobile SoCs, data centre accelerators, high-end networking |
| 5nm and below | $200M–$500M+ USD | ~50M+ units/year | Flagship mobile processors, HPC accelerators (NVIDIA H-series, AMD EPYC) |
⚠ Re-spin cost is the hidden risk multiplier: If a functional bug is discovered after tapeout that requires a new mask set, the NRE cost is effectively doubled (or more) and the schedule slips by 6–12 months at advanced nodes. At 28nm, a re-spin costs $2–10M in additional NRE and 6–9 months of delay. At 7nm, a re-spin costs $50–200M. Pre-tapeout verification investment — simulation, formal verification, FPGA prototyping, emulation — is the primary defence against re-spin risk and should be budgeted as a proportion of the mask set cost, not minimised as a schedule shortcut.
A custom ASIC programme progresses through a defined set of stages from specification to volume production. Typical duration: 18–36 months from specification freeze to qualified volume production for a standard cell design at 28nm–7nm. Each stage has defined entry and exit criteria that must be met before proceeding.
Requirements and Specification Definition
Define: functional requirements, performance targets (speed, power, area), interface specifications, operating conditions, reliability grade (commercial/industrial/automotive), cost targets, target process node, and volume forecast. A well-defined specification is the foundation for everything that follows — vague specifications produce schedule overruns and re-spins.
Spec freeze gateTarget node confirmed
Architecture Design
Define the IC's top-level architecture: block diagram, data flow, clock domains, memory architecture, interface protocols, power domains, and IP blocks to be licensed. Architecture decisions have the largest downstream impact on performance, area, power, and design effort — and are the least costly to change at this stage.
Block diagramIP selection
RTL Design (Register Transfer Level)
Engineers describe the logic circuit behaviour in Verilog or VHDL — the hardware description languages that define logic as data transfers between registers. RTL is the primary design representation and the input to all subsequent verification and synthesis steps. Quality and completeness of RTL coding directly determines verification coverage and synthesis outcome.
Verilog / VHDLRTL freeze gate
Pre-Synthesis Verification
Confirms the RTL design correctly implements the specification before synthesis. Methods: functional simulation (testbench-driven stimulus-response comparison), formal verification (mathematical proof of correctness for specific properties), and FPGA prototyping (real-hardware execution at scale for software co-development). Verification is typically the most time-consuming stage — insufficient verification investment is the primary cause of post-silicon re-spins.
SimulationFormal verificationFPGA prototype
Logic Synthesis
EDA synthesis tools (Synopsys Design Compiler, Cadence Genus) convert the RTL description into a gate-level netlist — a network of standard cells from the foundry library connected according to the logic function. Synthesis optimises for the target constraints: timing (setup/hold margins), power, and area.
Gate-level netlistTiming closure estimate
Physical Design (Place and Route)
The gate-level netlist is converted to a physical layout — cells are placed on the silicon floorplan and metal interconnects are routed between them. This is the "back end" of ASIC design. Physical design must satisfy timing, power, signal integrity, and DRC (design rule check) constraints simultaneously. Advanced node physical design can take 3–6 months for complex designs.
FloorplanPlace and routeDRC clean
Post-Layout Verification and Sign-Off
Verifies physical layout meets all constraints: STA (static timing analysis) confirming all timing paths meet setup and hold margins at all process/voltage/temperature corners, LVS (layout vs. schematic) confirming layout matches netlist, DRC (design rule check) confirming layout meets foundry manufacturing rules, and power analysis confirming IR drop and electromigration limits are satisfied.
STA sign-offLVSDRCTapeout gate
Tapeout
The final GDS (Graphic Design System) file representing the complete physical layout is delivered to the foundry. The foundry uses this data to create photomasks — one mask per layer (typically 30–100+ layers at advanced nodes). This is the financial commitment point: the mask set cost is incurred at tapeout. Once masks are cut, this NRE cannot be recovered.
NRE committedPoint of no return
Wafer Fabrication
The foundry manufactures silicon wafers using the photomasks — typically 300mm wafers containing hundreds to thousands of identical die. Fabrication cycle time varies by process: 8–16 weeks at mature nodes, 12–20 weeks at leading-edge nodes. The first engineering wafers (E-samples) are typically a small lot (1–3 wafers) used for initial characterisation.
8–20 week cycleE-sample wafers
Packaging
Wafers are diced into individual die; each die is attached to a substrate, wire-bonded or flip-chip-bonded to the package, and encapsulated. Package options range from traditional QFP and BGA to advanced 2.5D (interposer-based) and 3D stacking for leading-edge products. Packaging is typically performed at a separate OSAT (Outsourced Semiconductor Assembly and Test) supplier.
OSAT supplierPackage qualification
Electrical Test and Characterisation
First-silicon characterisation: verify DC parameters at all specified corners, AC performance including timing and frequency, functional test of all design features, and correlation with simulation predictions. Identify any silicon bugs (silicon errata). Make the go/re-spin decision: if bugs are found, assess whether they are acceptable for the application or require a mask fix (metal ECO) or full re-spin.
First siliconGo/no-go gateRe-spin risk
Qualification and Volume Production
Complete reliability qualification (JEDEC stress tests, AEC-Q100 for automotive): HTOL, ESD, latch-up, moisture sensitivity, mechanical shock and vibration. After qualification sign-off, ramp volume production with committed wafer starts, final test at OSAT, and outgoing quality inspection. Establish supply chain for steady-state volume supply.
JEDEC qualificationVolume ramp
FABLESS
Design only — no manufacturing
Designs ICs but owns no fabrication equipment. Sends GDS layout data to an independent foundry for manufacturing. No capital equipment to maintain. Can choose the optimal foundry and process node for each design. Dominant model for new IC companies — capital-efficient and focused on design value.
Examples: Apple, NVIDIA, Qualcomm, AMD, MediaTek, Marvell, Broadcom, HiSilicon.
FOUNDRY
Manufacturing only — for others' designs
Manufactures ICs from customers' design data. Does not design its own products. Invests entirely in manufacturing technology — process node advancement, yield improvement, capacity. Achieves utilisation and process expertise levels no captive fab could match. TSMC alone manufactures chips for hundreds of fabless companies.
Examples: TSMC (Taiwan), Samsung Foundry, GlobalFoundries (US), UMC (Taiwan), SMIC (China).
IDM
Integrated — design + manufacturing
Designs and manufactures its own ICs in its own fabs. Full vertical integration provides process design co-optimisation advantage but requires massive capital investment to maintain leading-edge fabs. Increasingly rare at leading-edge nodes due to the multi-billion-dollar fab investment requirement.
Examples: Intel, Samsung Semiconductor, Texas Instruments, Infineon, STMicroelectronics.
Geopolitical concentration risk in foundry selection: TSMC manufactures approximately 60–65% of all global foundry revenue and an even higher share of advanced node (7nm and below) production. Samsung Foundry is the only other company currently operating advanced node production at scale. This geographic concentration — both leading-edge foundries are in Taiwan or South Korea — is a supply chain risk that every company designing advanced-node ASICs must address explicitly in their supply continuity planning. For designs using mature nodes (28nm and above), GlobalFoundries, UMC, SMIC (with export control considerations), and STMicro's foundry operations provide geographic diversification options.
DESIGN HOUSES
Custom IC design services
Design houses provide ASIC design services to companies that have a product concept and funding but lack in-house IC design capability. Services range from full design (RTL to GDS) to partial (verification only, physical design only, DFT). Major design houses: Faraday Technology (Taiwan), Open-Silicon (US, now owned by SiFive), eMemory (Taiwan), Verisilicon (China). Engagement model: NRE payment (typically milestone-based) for defined deliverables. IP ownership must be explicitly negotiated — the default in many design house agreements is that the foundry GDS belongs to the customer but the design methodology and any reusable IP belongs to the design house.
IP VENDORS
Licensed IP blocks for IC integration
IP vendors sell pre-designed, pre-verified IP blocks that design teams integrate into their ASIC rather than designing from scratch. Arm: the dominant CPU core IP vendor; Cortex-M, Cortex-A, and Cortex-R cores used in the majority of custom SoCs. Synopsys: DesignWare — the industry standard for interface PHYs (PCIe, USB, DDR), memory compilers, and security IP. Cadence: Tensilica (DSP/AI cores), Verification IP. CEVA: wireless connectivity and DSP cores for IoT and audio. SiFive: RISC-V CPU cores. Imagination Technologies: GPU IP. IP licensing models: upfront licence fee + per-unit royalty (typically $0.01–$0.50 per chip depending on IP value) + annual maintenance.
Custom IC design requires specialised EDA (Electronic Design Automation) software for every stage — synthesis, simulation, formal verification, place and route, static timing analysis, DRC/LVS, and power analysis. No custom ASIC programme can proceed without appropriate EDA tool access.
BIG THREE EDA VENDORS
Synopsys, Cadence, Siemens EDA
Synopsys, Cadence Design Systems, and Siemens EDA (acquired Mentor Graphics in 2017) collectively represent approximately 75% of the global EDA market and provide the tools used in the majority of ASIC designs worldwide. Their tools are required for foundry-qualified sign-off at leading-edge nodes — alternative tools are not accepted for sign-off by TSMC, Samsung, or GlobalFoundries at advanced nodes. Annual EDA tool licences: typically $5M–$50M USD per year for a full professional ASIC design toolkit, scaling with team size and tool scope.
CLOUD / ACCESSIBLE OPTIONS
Synopsys Cloud, Cadence Cloud, open-source EDA
Cloud-based EDA platforms (Synopsys Cloud, Cadence Orion Cloud) provide access to professional tools on a per-hour or subscription basis — removing the upfront capital barrier for startups and smaller companies that cannot justify perpetual licence investment for a single design project. Open-source EDA tools (OpenROAD, KLayout, Yosys) are increasingly capable for mature-node designs (130nm, 180nm) and are used by research and educational institutions. They are not yet accepted for production sign-off at leading-edge foundries but are appropriate for prototyping and initial exploration.
ASIC procurement extends far beyond standard component purchasing. The procurement team has a substantive strategic role in programme structure, contract negotiation, and supply chain management throughout the development cycle — not just at the point of volume production.
ROLE 1
NRE contract negotiation
Structure the NRE agreement with the design house: total NRE amount, milestone payment schedule tied to verified deliverables (RTL freeze, netlist, sign-off, tapeout, first silicon characterisation), acceptance criteria for each milestone, IP ownership provisions (who owns the GDS, who owns reusable IP blocks, portability rights), liability and re-spin cost responsibility, and termination provisions. Milestone-based payment aligned with risk events — not calendar-based — is the standard best practice.
ROLE 2
Foundry qualification and contract
Select and qualify the foundry against technical capability, geopolitical risk profile, capacity availability, and customer support quality. Negotiate the foundry supply agreement: wafer pricing (at specified volumes), capacity reservation (committed wafer starts per quarter), yield guarantees, expedite rights, long-term price escalation limits, and supply continuity provisions. Foundry contracts are long-term agreements — the first negotiation sets the framework for the product's entire lifecycle.
ROLE 3
IP vendor licence negotiation
Negotiate licence terms with each IP vendor: upfront licence fee, per-unit royalty structure, field-of-use definition (product category, geography, end market), warranty and support terms, upgrade rights for new process nodes, and indemnification scope for IP infringement claims. IP costs are a significant portion of total NRE — negotiate all licences before design start to have certainty on total programme cost.
ROLE 4
OSAT (packaging and test) supply chain
Manage the packaging, assembly, and test supply chain separately from the foundry — most advanced packaging and test operations are performed at specialist OSAT companies (ASE Group, Amkor, JCET). Negotiate test time pricing, burn-in capacity, final quality specification, and supply lead times. For advanced packaging (2.5D, 3D), substrate procurement is a separate supply chain element requiring its own qualification and contracting.
ROLE 5
Demand forecasting and supply planning
Custom IC supply chains have long lead times — wafer start to packaged IC delivery is typically 12–18 weeks. Foundry capacity is committed via wafer start forecasts, typically 12–26 weeks in advance. Procurement must build a demand forecasting process accurate enough to commit wafer starts without either starving production (under-forecasting) or accumulating costly work-in-process inventory (over-forecasting). Forecast accuracy has direct financial consequences in ASIC supply chains that it does not have for standard-component purchasing.
DESIGN RISK
Silicon bugs requiring re-spin
A functional bug found after tapeout can double NRE cost and add 6–12 months to the schedule. Mitigation: intensive pre-tapeout verification (simulation coverage metrics, formal verification, FPGA prototyping), mandatory independent design review checkpoints, DFT (Design for Test) insertion enabling post-silicon debug, and conservative timing and power margins that create tolerance for process variation. Budget for verification at 30–50% of total design labour time — not less.
FOUNDRY / SUPPLY RISK
Capacity, yield, geopolitical disruption
Foundry supply can be disrupted by: capacity allocation shifts to higher-priority customers, yield problems on a specific process layer, natural disasters affecting fab operations (TSMC has experienced earthquake-related disruptions), or geopolitical restrictions on advanced node access (US export control on Chinese foundries). Mitigation: capacity reservation contracts, dual-source evaluation at process node selection, strategic wafer inventory building, and supply continuity clauses in foundry agreements.
INTELLECTUAL PROPERTY RISK
Patent infringement and IP ownership disputes
An ASIC integrating circuit techniques that infringe third-party patents creates financial and legal exposure that can exceed the ASIC NRE. Mitigation: FTO (Freedom to Operate) analysis before tapeout covering known patent holders in the relevant technology areas; clear IP ownership provisions in all development contracts with design houses; full indemnification clauses from IP vendors for the IP blocks they license; and patent monitoring throughout the product lifecycle.
VOLUME / BUSINESS RISK
Insufficient volume to recover NRE
If product volume does not reach the break-even level, NRE is not recovered and the ASIC programme produces a net financial loss relative to the FPGA or standard component alternative. Mitigation: conservative volume projections in the business case (not optimistic); structured ASIC or FPGA alternatives defined for volume risk scenarios; phased programme development with go/no-go gates at key milestones (architecture, RTL freeze, tapeout approval) based on updated volume and market data; and NRE cost sharing with distribution or manufacturing partners where feasible.
Summary
Custom IC and ASIC procurement is a strategic long-term investment that delivers returns measured in competitive differentiation, supply independence, performance, and integration — not in the standard procurement metrics of unit cost reduction and lead time management. Match IC type to volume and NRE budget: FPGA for development and lower-volume products, structured ASIC for medium-volume programmes, standard cell ASIC for high-volume products where performance and cost justify multi-million NRE. NRE scales dramatically with process node — 28nm is the practical threshold for programmes with <$10M NRE budget. The 12-step development flow from specification to volume production typically takes 18–36 months. The fabless/foundry model is dominant — select foundries based on technical capability and geopolitical risk profile. Use design houses when in-house design capability is absent. Negotiate IP licences before design start. The procurement team's role spans NRE contracting, foundry qualification, IP licensing, OSAT supply chain, and demand forecasting — not just volume production purchasing. Pre-tapeout verification investment is the highest-ROI risk mitigation in any ASIC programme: the cost of a re-spin at advanced nodes dwarfs any verification cost savings.