HDI build-up structure types and when to use each (1+N+1, 2+N+2, 3+N+3); the four specification categories you must communicate clearly to avoid misquotes and defects; a mandatory equipment checklist for evaluating HDI manufacturers; how to use cross-section analysis to verify quality before committing to production; and five concrete strategies to reduce HDI board cost without compromising functionality.
HDI PCBs achieve high routing density through two key features: microvias — drilled holes typically 0.15 mm diameter or smaller, enabling connections between adjacent layers without consuming the through-board space of a conventional via — and fine patterns, with trace/space down to 75 µm or below. These features allow the same circuit functionality to be realized in a significantly smaller board footprint.
Build-Up Structure Classification
The notation X+N+X describes how many sequential build-up layers are added on each side of the core board (N). Each build-up stage adds one pair of copper/dielectric layers and requires an additional lamination, laser drilling, and plating cycle.
1+N+1
One Build-Up Layer per Side
Core board with one additional layer built up on each side. The entry point for HDI. Adds blind vias connecting layer 1 to layer 2 (and layer N to N+1 on the back). Suitable for moderate density increases over standard multilayer.
Wearables · mid-range phones · industrial modules
2+N+2
Two Build-Up Layers per Side
Two sequential build-up layers per side. Enables stacked microvias (vias stacked on top of each other across layers). Significantly higher routing density than 1+N+1. Manufacturing complexity and cost increase proportionally.
Flagship smartphones · high-end wearables · dense FPGA boards
3+N+3 and beyond
Three or More Build-Up Layers
Used in the most demanding applications. Each additional stage multiplies manufacturing steps, yield challenges, and cost. Required for fine-pitch BGA packages with ball pitches below 0.4 mm and advanced package-on-package assemblies.
Leading-edge mobile SoCs · semiconductor package substrates
Design principle: Use the minimum build-up count that your routing density actually requires. Moving from 1+N+1 to 2+N+2 is not just a cost increase — it adds manufacturing risk and extends lead time. Involve your PCB manufacturer in the design phase to validate whether a lower build-up count can be achieved with layout optimization before locking the structure.
HDI PCB quoting and manufacturing errors most frequently trace back to incomplete or ambiguous specifications. For each of the four categories below, text descriptions alone are insufficient — drawings and dimensional callouts are required.
1. Build-Up Structure and Stackup Drawing
Create a complete stackup drawing that documents: build-up layer count per side, core layer count and thickness, build-up dielectric material and thickness per layer, copper foil weight per layer, and total board thickness. Never communicate the stackup purely in text. A drawing eliminates interpretation ambiguity and gives the manufacturer a documented record to manufacture against and verify.
2. Microvia Specifications
For every microvia type in your design, specify all of the following:
| Via Type | Description | Key Parameters to Specify |
|---|
| Blind Via |
Connects an outer layer to an inner layer without going through the entire board. The most common microvia type in HDI. Drilled from one surface only — visible from one side |
Drilling diameter · Target landing pad layer · Fill method |
| Buried Via |
Connects two or more inner layers without reaching either outer surface. Requires pre-lamination drilling before the outer layers are added. Not visible on finished board surface |
Layer span (e.g., L3–L4) · Fill method · Pre-lamination or laser |
| Skip Via |
A blind via that skips over an intermediate layer, connecting non-adjacent layers from the surface. Requires controlled-depth laser drilling — process-intensive |
Layer span · Drilling diameter · Depth control tolerance |
| Via-in-Pad |
Microvia placed directly within a surface mount pad rather than adjacent to it. Essential under fine-pitch BGAs. ⚠ Requires fill AND planarization — must be explicitly specified |
Fill method (resin / copper) · Planarization required: YES/NO · Over-plating spec |
Via-in-pad without fill and planarization causes solder joint failure: If a via-in-pad is not properly filled and the surface ground flat (planarized), the solder paste deposited on the pad will flow into the void during reflow — collapsing the joint or causing a short to an adjacent pad. Always mark via-in-pad locations explicitly on your fab drawing and specify fill + planarization as a hard requirement, not an option.
3. Fine Pattern Requirements
- Minimum trace width and space: State the tightest trace/space value anywhere in the design. Below 75 µm, confirm the manufacturer's process capability before sending design files. Below 50 µm, only a subset of HDI manufacturers can reliably comply.
- Layer-specific requirements: If only certain layers have fine patterns, identify them explicitly. Manufacturers may apply different process flows or inspection protocols to fine-pattern layers.
- Annular ring minimum: State the minimum copper annular ring around vias on each layer. Tighter annular rings require better registration accuracy and should be confirmed against the manufacturer's process Cpk data.
4. Impedance Control
For boards carrying high-speed signals, controlled impedance is a manufacturing requirement, not just a design target. Specify:
- Target impedance value(s) for each controlled line type (e.g., 50 Ω single-ended, 100 Ω differential)
- Tolerance — standard is ±10%; tighter tolerances (±5%) increase cost and require coupon-based measurement
- Which signal layers carry controlled-impedance traces — don't require impedance control on layers that don't need it
- Reference plane layers for each impedance-controlled layer, to allow the manufacturer to adjust dielectric thickness during stack-up optimization
HDI manufacturing quality is a direct function of process experience and equipment capability. A manufacturer that is strong on standard multilayer boards is not automatically qualified for HDI. Evaluate them specifically on the following criteria.
Mandatory In-House Equipment
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Laser Drill (CO2 and/or UV)
CO2 laser ablates the dielectric to form the microvia cavity. UV laser can drill directly through copper for finer vias. Required for any build-up layer with microvias.
⚠ Mechanical drilling cannot make microvias — this is non-negotiable
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LDI (Laser Direct Imaging)
Projects circuit patterns directly from digital files onto photoresist, eliminating the registration error inherent in film-based exposure. Essential for fine-pattern layers where registration tolerances are tight.
⚠ Film-based exposure is inadequate for fine patterns below ~100 µm
⚗️
Plasma Desmear
Removes the resin smear that laser drilling leaves on the via floor and walls. Without proper desmear, copper plating adhesion in the via is compromised, causing reliability failures under thermal cycling.
⚠ Chemical desmear alone is often insufficient for small-diameter microvias
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Via Fill Equipment
Required when via-in-pad is present. Fills the via cavity with resin or copper before planarization grinding. Must be followed by copper over-plating to ensure a flat, solderable surface.
⚠ If via-in-pad is in your design, confirm fill capability explicitly
In-house vs. outsourced: A manufacturer who outsources laser drilling, desmear, or via fill to a subcontractor loses direct visibility into those process steps. This weakens quality control at precisely the most critical points in HDI manufacturing. Prefer manufacturers who operate all critical HDI processes under one roof.
Experience Verification
HDI manufacturing is not a capability that transfers automatically across build-up counts. Ask these questions directly:
- Specific build-up experience: "Have you produced boards with [your build-up count]? Can you share a reference customer in a similar industry?" A manufacturer comfortable at 1+N+1 may have limited experience at 2+N+2.
- Stack via capability: If your design uses stacked microvias (a via directly on top of another via across consecutive build-up layers), confirm the manufacturer has demonstrated reliable stacked via quality. This is one of the most challenging HDI processes to control.
- Fine-pattern production Cpk: For trace/space below 75 µm, ask for process capability data (Cpk values) rather than just a stated minimum. A Cpk of 1.33 or above on the critical dimension is a meaningful indicator of process control.
Cross-Section Analysis: The Only Way to Verify HDI Quality
External visual inspection and electrical testing can verify continuity but cannot reveal the internal quality of microvias or build-up layers. Before approving transfer to production, require a cross-section (microsection) analysis report from the first article samples.
- Microvia plating thickness: Measure copper plating on the via sidewall and bottom. IPC-6012 Class 2 requires a minimum of 20 µm average. Thin plating at the via bottom is a common HDI failure mode under thermal cycling.
- Via fill condition: Confirm the fill material completely occupies the via with no voids or shrinkage gaps. Voids in filled vias cause solder collapse during reflow (via-in-pad) or cracking under thermal stress.
- Layer-to-layer registration: Measure the offset between microvia landing pads and the target pad on the adjacent layer. Excessive offset reduces the effective annular ring and can cause opens or intermittent connections.
- Build-up layer thickness uniformity: Measure dielectric thickness consistency across the cross-section sample. Non-uniform dielectric thickness causes impedance variation and is a sign of process instability.
What to request from the manufacturer: A cross-section report should include polished cross-section photographs at defined locations on the board (typically at least one via from each build-up layer), with dimensional measurements overlaid. Request the report as a PDF with calibrated scale bars in the images. This documentation also becomes part of your design qualification record.
HDI boards inherently cost more than standard multilayer boards due to the additional process steps. But many HDI designs include unnecessary complexity that adds cost without contributing to product function. These five strategies address the most common areas for optimization.
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1. Minimize Build-Up Stage Count
Each additional build-up stage roughly doubles manufacturing complexity and adds significant cost. Before finalizing the build-up count, run the routing to completion at a lower count. If 1+N+1 achieves acceptable routability with minor board size or layer count adjustment, avoid 2+N+2. Involve the manufacturer's engineering team early — they can often propose routing strategies that reduce the required build-up.
Potential saving: 20–40% cost reduction by eliminating one build-up stage
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2. Use Standard Microvia Diameters
Manufacturers have optimized their laser drill processes for specific via diameters — typically 0.10 mm and 0.15 mm. Specifying a non-standard diameter like 0.075 mm may require process adjustment, slower cycle times, or reduced yield. Unless your design has a specific requirement for a non-standard diameter, use the manufacturer's standard sizes.
Potential saving: 5–15% on drilling cost; also improves yield
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3. Maximize Panel Utilization
Manufacturers process HDI boards on fixed-size panels. The per-board cost is directly proportional to how much panel area each board occupies. Before finalizing the board outline, ask the manufacturer for their standard panel size and optimize your board dimensions and array arrangement to maximize pieces per panel. A 10% improvement in panel yield translates directly to lower unit cost.
Potential saving: 10–25% depending on board shape and size
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4. Only Require Impedance Control Where Necessary
Impedance-controlled layers require coupon fabrication, TDR measurement, and in some cases iterative stackup adjustment. Apply impedance control specifications only to layers that actually carry controlled-impedance signals. Layers carrying only power, ground, or non-critical slow signals do not need impedance control callouts — adding them unnecessarily increases cost and processing complexity.
Potential saving: reduces controlled-impedance NRE and adds production flexibility
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5. Align Design Decisions with Manufacturing Constraints Early
The most expensive time to discover a design-manufacturing mismatch is after the Gerbers are approved. Share a preliminary stackup and via strategy with your manufacturer at the concept stage and ask for a DFM review. Common catches: stacked via structures that require costly process adjustments; minimum annular rings too tight for the manufacturer's registration capability; or pad-to-via spacing violations in the fine-pattern layers.
Potential saving: avoids costly respins and re-qualification cycles
Prototype supplier vs. production supplier: For HDI, the gap between prototype capability and production volume capability can be significant. A prototype house may offer faster NPI turns but lack the process control for high-volume yield. If you prototype at one manufacturer and produce at another, do a full cross-section qualification at the production supplier before ramping — don't assume that identical-looking Gerbers will produce identical internal structure.
Key Takeaways
Successfully procuring HDI PCBs comes down to three disciplines applied consistently: specification clarity — always provide a stackup drawing, explicit via fill callouts, and layer-level pattern requirements rather than relying on text descriptions; supplier qualification — verify in-house equipment (laser drill, LDI, plasma desmear, via fill), build-equivalent production experience, and stacked-via capability before committing; and quality verification — require cross-section analysis on first articles to confirm plating thickness, fill condition, registration, and layer uniformity before approving production transfer. Combined with the five cost strategies — minimizing build-up stages, using standard via sizes, maximizing panel yield, scoping impedance control, and engaging manufacturers at the design stage — this approach reduces both cost and risk.