PCB Design & Procurement Guide

EMC / EMI Design Basics:
Key Principles for the Design Stage

EMC failures discovered at the certification lab are among the most expensive problems in electronics product development. Design changes at that stage cost orders of magnitude more than the same fix applied during layout. This guide covers the five design-stage techniques that prevent most EMC failures, the test types that determine regulatory compliance, and the systematic approach when failures occur anyway.

FCC / CE / CISPR 9 min read Design + Troubleshooting

This guide covers: the distinction between EMC, EMI, emission, and immunity — and why it matters for design decisions (POINT 01); the primary EMI sources in a typical electronic product (POINT 02); the five design techniques that address the majority of EMC problems at the source (POINT 03); the regulatory standards and test types that govern market access (POINT 04); and the systematic troubleshooting methodology when a product fails an emission test (POINT 05).

POINT 01

EMC, EMI, Emission, and Immunity — The Terminology That Shapes Your Design Decisions

The terms EMC and EMI are often used interchangeably in casual engineering discussion, but they describe different things — and the distinction matters when you are prioritising design effort or interpreting test results.

EMC (Electromagnetic Compatibility) is the property of a complete system: the ability to operate correctly in its intended electromagnetic environment without causing unacceptable interference to other equipment. EMC is the goal. It has two aspects that must both be satisfied: emission performance and immunity performance.

Emission is the extent to which a device radiates or conducts unwanted electromagnetic energy into its environment. The regulatory limits for emission — FCC Part 15, CISPR 32, EN 55032 — define the maximum levels of electromagnetic noise a device is permitted to generate. A device that exceeds these limits cannot be legally sold in the regulated market, regardless of how well it performs functionally.

Immunity (also called susceptibility) is the extent to which a device maintains correct operation when subjected to externally applied electromagnetic disturbances — whether from adjacent equipment, lightning-induced transients, electrostatic discharge, or intentional radiated fields. Immunity testing verifies that the device does not malfunction under defined levels of external interference.

EMI (Electromagnetic Interference) refers specifically to the unwanted electromagnetic energy — the noise — that a device emits. EMI is what you measure during an emission test; EMC is the broader property that encompasses both the emission behaviour and the immunity behaviour of the complete product.

Why the distinction matters for design priority: Emission and immunity problems generally have different root causes and different design solutions. Emission problems most frequently trace back to high-frequency switching currents and the loops they form — ground plane gaps, long return paths, and poorly placed bypass capacitors. Immunity problems more frequently involve inadequate filtering at I/O ports, ESD protection gaps, and insufficient supply rail decoupling. Understanding which dimension you are designing for — and which you are testing for — prevents the common mistake of applying immunity solutions to emission problems and vice versa.
POINT 02

Primary EMI Sources — Where the Noise Originates

No electronic product is free of EMI sources. The question is whether those sources generate noise within the regulatory limits for your target market. Understanding which circuit elements are the dominant EMI sources in a typical design allows you to direct design attention — and PCB layout effort — to the places where it will have the greatest impact.

⚡
Switching Power Supplies
DC-DC converters, buck/boost regulators, and AC adapters. The switched current generates broadband harmonics at multiples of the switching frequency. Often the dominant EMI source in a product. Both conducted (onto the supply rails) and radiated emissions.
🕐
Clock Signals and High-Speed Digital
Periodic clocks generate strong narrowband emissions at the fundamental and harmonics. High-speed buses (USB, PCIe, DDR, Ethernet) add broadband content from data transitions. Fast rise times create high-frequency content far above the nominal clock frequency.
🔄
Motor Drive Circuits
PWM motor control generates conducted and radiated noise at the PWM frequency and harmonics. Brushed DC motors add broadband noise from commutator switching. Stepper and BLDC drivers produce structured harmonic spectra.
📡
Wireless / RF Circuits
Intentional transmitters (Wi-Fi, Bluetooth, cellular, LoRa) generate high-level signals at their operating frequency. These are managed through regulatory type-approval of the radio module, but spurious emissions from the RF front-end can still exceed limits.
📏
Long Traces and Cables
Any conductor that is a significant fraction of a wavelength at the noise frequency acts as an antenna. I/O cables are particularly effective radiators because they extend beyond the PCB and bypass the product enclosure. Filtering at the point where cables exit the enclosure is the primary mitigation.
⚠ The most common design error: Designing a PCB with EMI sources far from their loads — a switching converter placed at one corner of the board, switching current flowing through long traces to the output capacitor, with the return current forced through a long ground path. Every centimetre of that loop radiates proportionally to the enclosed area. Minimising switching loop area is the single most effective layout measure for power supply EMI — and it costs nothing if implemented during initial layout rather than as a retrofit.
POINT 03

Five Design Techniques That Prevent Most EMC Failures

The five techniques below address the root causes of the majority of emission failures. They are ordered by their cost-effectiveness: the first two are free to implement correctly and the most impactful; the last two involve component cost but can be applied after layout is complete if the earlier measures prove insufficient.

TECHNIQUE 01
Ground Plane — Continuous, Adjacent, and Complete
A solid, continuous ground plane is the single most effective EMC design measure. Its function is to provide a low-impedance return path for every signal and power current that flows directly beneath the source trace — keeping the current loop area as small as physically possible. Every interruption in the ground plane — a slot, a via escape route that splits the plane, a cutout for mechanical clearance — forces return current to take a longer, indirect path, increasing the effective loop area and the radiated emission proportionally. Design rules: dedicate at least one layer entirely to ground with no routing; never route signal traces across a gap in the ground plane; keep the ground plane layer adjacent to all signal layers (the benefit of a ground plane decreases with distance); and avoid star-pattern return routing that creates long ground paths.
Dedicated ground layerNo traces across plane gapsAdjacent to signal layersNo ground plane cuts
TECHNIQUE 02
Bypass Capacitors — Placed at the Pin, Not Near the IC
Bypass (decoupling) capacitors filter high-frequency noise from power supply pins by providing a local charge reservoir for transient currents, preventing those transients from propagating through the power distribution network. Their effectiveness is determined almost entirely by placement — specifically, by the size of the loop formed by the capacitor, its vias, and the IC power pin. A 100 nF capacitor placed 5 mm from the IC pin may provide 10–20 dB less decoupling than the same capacitor placed 0.5 mm from the pin. Placement rule: the bypass capacitor body must be between the IC power pin and the ground plane via, as close to the pin as physically possible. The ground return via belongs directly beneath the capacitor pad — not routed back through a shared via or a long trace. Use a small high-frequency capacitor (100 nF ceramic, X7R) closest to the pin; add a larger bulk capacitor (1–10 µF) slightly further away for lower-frequency supply noise.
0.5 mm from power pinGround via under cap pad100 nF nearest pin1–10 µF bulk further
TECHNIQUE 03
High-Speed Signal Routing — Short, Terminated, and Referenced
Clock and high-speed digital signal lines are EMI sources in proportion to their rise time, their length, and whether they have a low-impedance return path directly beneath them. Design rules: route clock lines as short as possible — a 10 cm clock trace radiates significantly more than a 2 cm trace at the same frequency; never route clock or high-speed lines over a gap in the ground plane or between two different reference planes; add series termination resistors (22–100 Ω typical) at the driver output to slow edge rates to the minimum required by the receiver — edge rate reduction of 2× reduces high-frequency emissions by approximately 6 dB; use differential signalling (LVDS, differential USB, differential Ethernet) wherever possible — differential pairs have inherently lower common-mode emission because the opposing currents cancel. Keep clock lines away from I/O connectors — a clock signal coupled onto an I/O cable becomes a highly effective radiating antenna.
Shortest possible routeNever cross plane gapsSeries terminationDifferential signallingAway from I/O connectors
TECHNIQUE 04
Shielding — Effective Only When the Perimeter Is Sealed
Metal shielding — whether a product enclosure, a PCB shield can over a noisy sub-circuit, or a shielded cable — can provide 20–60 dB of attenuation when implemented correctly. The critical limiting factor is apertures. Any opening in the shield that is larger than approximately λ/10 at the frequency of concern becomes an effective radiating slot antenna. A 15 mm slot in a shield is nearly transparent above 2 GHz. Shield design rules: ensure complete, continuous conductive contact between the shield and the ground plane around the entire perimeter — no gaps, with conductive gasket material at any joint that cannot be mechanically perfect; minimise aperture dimensions — necessary ventilation holes should be replaced by multiple small holes rather than one large opening; connector cutouts should be as small as the connector allows; and verify that the shield mounting pads make good electrical contact to the ground plane with multiple closely-spaced vias.
Continuous perimeter contactApertures < λ/10Conductive gaskets at gapsMultiple small holes preferred
TECHNIQUE 05
EMC Filter Components — Targeted at Port Boundaries
Ferrite beads, common-mode chokes, and multi-stage LC EMI filters are the primary tools for attenuating conducted emissions and preventing I/O cable radiation. Ferrite beads on DC power lines suppress high-frequency switching noise from propagating to adjacent circuits or to the supply rails. Common-mode chokes on differential signal I/O lines (USB, Ethernet, RS-485) attenuate common-mode noise — the noise component that actually drives radiation from cables — while allowing the differential signal to pass. Placement is critical: all EMC filters must be placed at the port boundary — where the cable or connector meets the PCB — before any signal routing into the board interior. A filter placed in the middle of a signal trace is partially effective; a filter placed after the route has already coupled noise to other traces is ineffective. Select ferrite bead impedance based on the noise frequency: the bead's rated impedance applies only at its specified frequency (typically 100 MHz) — verify impedance at the actual problem frequency using the manufacturer's frequency-impedance curve.
At port boundaryFerrite bead on DC linesCommon-mode choke on I/OImpedance vs. frequency curve
POINT 04

Regulatory Standards and EMC Test Types

Market access for electronic products in most major markets requires passing a formal EMC test conducted at an accredited laboratory. The applicable standard depends on the target market and product category. Understanding which tests apply to your product — and what each test measures — allows you to design specifically for the tests that matter for your intended market.

Applicable Standards by Market

FCC Part 15
United States — FCC
Governs unintentional radiators in the US market. Class A (commercial/industrial) and Class B (residential) limits — Class B is more stringent. Self-certification is permitted for many Class B devices; FCC accredited lab testing required for Class A and for devices with intentional radiators.
EMC Directive
EU — 2014/30/EU + EN 55032
CE marking for the EU market requires compliance with the EMC Directive. Harmonised standard EN 55032 (CISPR 32) covers multimedia equipment emission. EN 55035 covers immunity. EN 61000-4 series covers specific immunity tests (ESD, EFT, surge). Notified body involvement varies by product category.
VCCI
Japan — Voluntary Control
Japan's voluntary EMC compliance scheme for information technology equipment. Class A and Class B limits similar to CISPR. Self-declaration based on VCCI test procedures. Separate mandatory requirements apply to certain product categories under Japan's Radio Law and Electrical Appliance and Material Safety Law.
CISPR 25
Automotive — Vehicle EMC
Defines limits for vehicles, boats, and internal combustion engines. Component-level testing for automotive electronics follows OEM-specific standards (e.g., Ford ES-XW7T, GM GMW3097) or ISO 11452 series for immunity. IATF 16949 supply chain requirements add quality system obligations.
IEC 60601-1-2
Medical Devices — IEC
Defines EMC requirements for medical electrical equipment. Significantly more stringent immunity requirements than EN 55035, reflecting the patient safety implications of immunity failures. 4th edition applies enhanced requirements for immunity to wireless transmitters in the environment of use.
EN 61000-4 Series
EU Immunity Test Methods
IEC/EN 61000-4-2: ESD (electrostatic discharge). 61000-4-3: radiated immunity. 61000-4-4: electrical fast transient / burst. 61000-4-5: surge. 61000-4-6: conducted immunity. 61000-4-8: power frequency magnetic field. Each specifies test level, test equipment, and pass/fail criteria.

The Core EMC Test Types — What Each Measures

Test NameAbbrev.What It MeasuresTypical Design Fix if Failing
Radiated Emission RE Electromagnetic field radiated through space from the device and its cables. Measured at 3 m or 10 m in a semi-anechoic chamber. Ground plane gaps; clock/switching loop area; cable filtering at I/O ports
Conducted Emission CE Noise conducted from the device back onto the AC mains or DC supply lines. Measured with a LISN (Line Impedance Stabilisation Network). Input filter on power supply; differential and common-mode filter components; bypass capacitors
Radiated Immunity RI Device's ability to continue operating correctly when exposed to an externally applied electromagnetic field (typically 80 MHz – 6 GHz). I/O cable filtering; board-level shielding; firmware handling of transient communication errors
ESD ESD Device's ability to survive contact and air discharge events (typically ±2 kV to ±8 kV). IEC 61000-4-2. ESD protection diodes at exposed pins; improved enclosure bonding; PCB layout changes to reduce ESD coupling paths
Electrical Fast Transient / Burst EFT Device's ability to operate correctly when the supply or I/O lines are subjected to bursts of fast, repetitive transients (IEC 61000-4-4). Common-mode chokes and X/Y capacitors at power input; ferrite beads on I/O lines; firmware error recovery
Surge Surge Device's ability to survive high-energy transients simulating indirect lightning strikes or switching transients on mains (IEC 61000-4-5). MOVs, TVS diodes, and gas discharge tubes at power input; line-to-line and line-to-ground protection components
The value of pre-scan testing: A pre-scan is an informal emission measurement conducted on a prototype in a non-accredited environment — a screened room, a near-anechoic space, or even a cleared lab bench using a near-field probe and spectrum analyser. Its purpose is not to predict the formal test result precisely, but to identify major emission peaks, correlate them to specific circuit nodes, and make design corrections before incurring the cost of a formal certification test session (typically $5,000–$20,000+ per session depending on the standard and laboratory). Products entering a formal certification test without pre-scan screening fail at significantly higher rates and require additional test sessions. A disciplined pre-scan programme — repeated after each significant design change — is the highest-return investment in the certification process.
POINT 05

Troubleshooting When the Test Fails — A Systematic Approach

An EMC test failure at the certification lab is not the end of the process — it is a data point that, interpreted correctly, tells you where to look. The systematic approach below converts a test failure into a targeted design fix rather than a panic-driven modification cycle that may fix one problem and create another.

01
Identify the Failing Frequency with Precision
Read the test report carefully for the specific frequency — or frequencies — where the emission exceeds the limit. A peak at 48 MHz is likely a 48 MHz system clock fundamental or a 24 MHz harmonic. A peak at 230 MHz in a product with a 500 kHz switching converter is probably the 460th harmonic. Matching the failing frequency to a known circuit source (clock, switching frequency, serial bus data rate) narrows the investigation to a specific circuit node before any physical measurement.
Frequency → sourceHarmonic analysis
02
Localise the Source with a Near-Field Probe
Connect a near-field magnetic probe to a spectrum analyser and scan the PCB surface — hold the probe a few millimetres above the board and observe the signal level at the failing frequency as you move across the board. Hot spots correspond to the physical location generating the strongest field. This step transforms the problem from "the product fails at 230 MHz" to "the switching converter output capacitor and inductor area is the primary source at 230 MHz." Localisation makes subsequent modifications targeted rather than speculative.
Near-field probeSpectrum analyserSpatial mapping
03
Apply the Lowest-Cost Fix First
Work through modifications in order of implementation cost. Ferrite bead on a signal line: cents, reversible, no PCB change. Additional bypass capacitor: cents, may require a hand-soldered placement. Series termination resistor value increase: cents. Shield can: dollars to tens of dollars, requires PCB footprint. Ground plane stitching via: requires PCB revision. Layout change: requires PCB revision. Board-level ground improvement: requires PCB revision. Apply one modification at a time and re-measure after each — stacking multiple changes simultaneously makes it impossible to attribute the effect to a specific modification.
One change at a timeLow cost firstRe-measure after each
04
Re-Measure the Full Spectrum After Each Modification
After any successful modification, always re-scan the full emission spectrum — not just the previously failing frequency. Adding a filter on one path can redirect noise to another path, making a previously marginal emission into a new failure. Adding a shield can change the resonant behaviour of the enclosure. Changing a termination resistor value affects signal integrity as well as EMC. Full-spectrum re-measurement after each change ensures that fixing one problem has not created another.
Full spectrum scanNot just failing frequencySecondary effects
05
If Component-Level Fixes Are Insufficient — Escalate to Layout
If ferrite beads, additional bypass capacitors, and shields do not bring the product into compliance, the root cause is almost certainly a layout issue — ground plane interruptions, large switching loops, or signal traces without adjacent ground return. These require a PCB revision. The most cost-effective point to identify and correct layout issues is before the first prototype is built, which is the argument for early pre-scan testing and for applying the design principles in POINT 03 from the beginning of layout. A PCB revision for EMC at the certification stage typically costs 6–10 weeks of project time in addition to the board cost — the same fix applied at the design stage costs one engineer one day.
PCB revision if neededRoot cause: layoutPrevention > retrofit

Summary

EMC/EMI performance is determined overwhelmingly at the design and layout stage — not at the certification lab. The five design techniques that prevent the majority of emission failures are: a solid, continuous ground plane that minimises return current loop area; bypass capacitors placed at the power pin with the shortest possible loop; high-speed signal traces routed short, terminated, and referenced to ground; shielding with a sealed perimeter and minimised apertures; and EMC filter components placed at port boundaries rather than mid-trace. The regulatory framework that governs market access varies by market (FCC Part 15 for the US, EN 55032 / EMC Directive for the EU, CISPR 25 for automotive) and requires passing emission and immunity tests at an accredited laboratory. The highest-return investment in the certification process is a disciplined pre-scan programme during prototype development — identifying and fixing emission peaks before the formal test dramatically reduces the cost and time of certification. When failures do occur, systematic troubleshooting — frequency identification, near-field source localisation, lowest-cost fix first, full-spectrum re-measurement — converts a test failure into a targeted correction rather than an expensive exploration cycle.

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